sureCore memory IP in Semidynamics’ RISC-V chip

Semidynamics is developing a high bandwidth, vector processing unit optimised for tensor processing aimed at AI applications. In order for AI to realise its full performance potential, the speed at which tensors are mathematically manipulated is critical.

To enable this, the vector compute units must be tightly coupled to a high-performance register file. Whilst this can be implemented via a standard synthesised approach, the outcome is often inefficient in terms of power and area.

sureCore memory IP in Semidynamics’ RIS-V chip

Semidynamics’ CEO, Roger Espasa, explained that sureCore was able to deliver performance exceeding 2.5GHz with compelling area and power characteristics. “Using a standard, synthesised, physical implementation flow would deliver the performance we need but at the expense of power and area,” he explained.

“Achieving the optimal configuration of Power, Performance and Area (PPA) is always the key goal in realising a chip design with the right market value proposition. This is why we went to sureCore to exploit their embedded memory expertise as this is fundamental to meeting our performance goals. In fact, it is a central feature of our highly parallel architecture that necessitates multiple instantiations of the high-performance register file to deliver the performance.”

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